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Type | Conference or Workshop Paper |
Scope | Discipline-based scholarship |
Published in Proceedings | Yes |
Title | Rethinking large-scale economic modeling for efficiency: optimizations for GPU and Xeon Phi clusters |
Organization Unit | |
Authors |
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Presentation Type | paper |
Item Subtype | Original Work |
Refereed | Yes |
Status | Published in final form |
Language |
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ISSN | 1530-2075 |
Event Title | IPDPS 2018 |
Event Type | conference |
Event Location | Vancouver, BC, Canada |
Event Start Date | May 21 - 2018 |
Event End Date | May 25 - 2018 |
Series Name | Proceedings - IEEE International Parallel and Distributed Processing Symposium |
Place of Publication | Vancouver |
Publisher | Institute of Electrical and Electronics Engineers |
Abstract Text | We propose a massively parallelized and optimized framework to solve high-dimensional dynamic stochastic economic models on modern GPU- and MIC-based clusters. First, we introduce a novel approach for adaptive sparse grid index compression alongside a surplus matrix reordering, which significantly reduces the global memory throughput of the compute kernels and maps randomly accessed data onto cache or fast shared memory. Second, we fully vectorize the compute kernels for AVX, AVX2 and AVX512 CPUs, respectively. Third, we develop a hybrid cluster oriented work-preempting scheduler based on TBB, which evenly distributes the time iteration workload onto available CPU cores and accelerators. Numerical experiments on Cray XC40 KNL “Grand Tave” and on Cray XC50 “Piz Daint” systems at the Swiss National Supercomputer Centre (CSCS) show that our framework scales nicely to at least 4,096 compute nodes, resulting in an overall speedup of more than four orders of magnitude compared to a single, optimized CPU thread. As an economic application, we compute global solutions to an annually calibrated stochastic public finance model with sixteen discrete, stochastic states with unprecedented performance. Index Terms—High-Performance Computing, Macroeconomics, Public Finance, Adaptive Sparse Grids, Heterogeneous Systems, CUDA, GPU, MIC |
Free access at | DOI |
Related URLs |
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Digital Object Identifier | 10.1109/IPDPS.2018.00070 |
Other Identification Number | merlin-id:16026 |
PDF File | Download from ZORA |
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Additional Information | © 2018 IEEE. |